Conventional read-write or “random access” memories (RAMs) include RAM cells arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells. That is, data words stored in the rows of conventional RAM cells are accessed by applying address signals to the RAM input terminals. In response to each write or read command a RAM receives, a data word is written to or read from a portion of the RAM array designated by the address.
In addition to the read-write capability of conventional RAMs, content addressable memories (CAMs) include memory cells that are selected in response to their content. Specifically, a CAM receives a (search key) data value that is compared with all of the (entry) data values stored in the many rows of the CAM. In response to each unique (search term) data value applied to the CAM input terminals, the rows of CAM cells within the CAM assert or de-assert associated match signals indicating whether or not the stored (entry) data values in that respective row of CAM cells matches the (search key) data value being searched by and applied to the CAM. CAMs are useful in many applications, such as search engines.
Similar to conventional RAM devices, CAM devices can either be formed utilizing dynamic random access memory (DRAM) cells, in which data values are stored using capacitors, or formed utilizing static random access memory (SRAM) cells, in which data values are stored using bistable flip flops.
FIG. 10 is a circuit diagram showing a conventional dynamic-based (DRAM-based) CAM cell 10, which includes a pair of one-transistor (1T) DRAM cells 12 and 16, and a four-transistor comparator circuit 14 made up of transistors Q3 through Q6. Each 1T DRAM cell 12 and 16 stores one bit of a two-bit data value that is compared with a two-bit data value transmitted on data lines D1 and D1-bar during search operations. DRAM cell 12 includes access transistor Q1 and a capacitor structure C1, which combine to form a storage node a that stores a first bit of data, and applies the stored data bit to the gate terminal of transistor Q3 of comparator circuit 14. Transistor Q3 is connected in series with transistor Q4, which is controlled by a data signal transmitted on inverted data line D1-bar, between a match line MATCH and a discharge line DISCHARGE. A second DRAM cell 16 includes access transistor Q2 and a capacitor structure C2, which combine to form a storage node b that stores a second data bit, and applies the stored data value to the gate terminal of transistor Q5 of comparator circuit 14. Transistor Q5 is connected in series with transistor Q6, which is controlled by a data signal transmitted on true (non-inverted) data line D1, between the match line and the discharge line.
During a data write operation (or during the write phase of a refresh operation), a data value to be stored is written to dynamic storage nodes a and b by applying appropriate voltage signals (e.g., VCC or ground) on bit lines BL1 and BL2, and then applying a high voltage signal on write word lines WL1 and WL2, which may be combined to form a single word line. The high voltage on write word lines WL1 and WL2 turn on transistor Q1 and Q2, thereby passing the voltage signals (data to be stored) to dynamic storage nodes a and b without Vt loss due to NMOS threshold voltage. Because the voltage signals are stored using capacitors C1 and C2 and the charge slowly leaks off, the stored data value decays over time. Refresh circuitry is required that periodically reads and rewrites (refreshes) the stored data value before it is lost.
This CAM cell can stores three different states, “1”, “0”, or “masked” (don't care). When the CAM cell stores the data value “1”, node “a” stores “1” and node “b” stores “0”. When the CAM cell stores the data value “0”, node “a” stores “0” and node “b” stores “1”. When the CAM cell is in masked (don't care) state, both node “a” and “b” store “0”. The data value stored at storage nodes a and b is applied to the gate terminals of transistors Q3 and Q5 of comparator circuit 14. Comparator circuit 14 is utilized to perform match (comparison) operations by precharging a match line MATCH and transmitting an applied data value on data lines D1-bar and D1 to the gate terminals of transistor Q4 and Q6, respectively. A no-match condition is detected when match line MATCH is discharged to ground through the signal path formed by transistors Q3 and Q4, or through the signal path formed by transistors Q5 and Q6 in any CAM cell connected to the match line. For example, when the stored data bit is “1” ,which means node “a” is “1” and node “b” is “0”, and the applied data signal is “0”, which means D1 is “0” and D1-bar is “1”, then both NMOS transistors Q3 and Q4 are turned on because both gate inputs, “a” and “D1-bar”, are logic “1”, to discharge match line MATCH to discharge line DISCHARGE when discharge line DISCHARGE is driven to a low voltage (e.g., ground). When a match condition occurs, match line MATCH remains in its precharged state (i.e., no signal path is formed by transistors Q3 and Q4, or transistors Q5 and Q6 in any of the CAM cells connected to the match line).
A problem with DRAM-based CAM 10 arises because of the construction of the capacitor C1 and C2 using a special multi-layer polysilicon fabrication process that significantly increases fabrication time and expense, which reduces the cost efficiency of smaller cell size. In addition to time and cost problems, thermal process step during polysilicon process reduces the transistor performance.
More significantly, conventional DRAM-based CAM cell 10 is limited in that a match (lookup or search) operation performed by comparator circuit 14 will be disturbed by a simultaneous read or refresh operation. When conventional DRAM cells 12 and 16 are refreshed (or read), the voltage on the storage node (a or b) initially shares its (positive or negative) charge with its associated bit line, which is precharged to about half of Vcc. If data in the cell is “1”, the voltage levels on both storage node and bit line after charge sharing become slightly higher than initial precharge level of bit line. If data in the cell is “0”, the voltage levels on both storage node and bit line after charge sharing become slightly lower than initial precharge level of bit line. The slight increase or decrease in bit line voltage is detected and amplified by a sense amplifier (not shown), which in turn drives the bit line high or low as needed to return the storage capacitor of the memory cell to its initial (undecayed) voltage. Between the time the charge from the storage capacitor is transferred to the bit line and the time the charge (voltage) is restored, comparator circuit 14 cannot be used for search operations because the voltage on the storage nodes (a and b) are about one-half of the system voltage, rather than being its normal logic level (i.e., either the system voltage or ground voltage). That is, the periodic refreshing needed by DRAM cells 12 and 16 interrupts search or lookup operations.
Accordingly, what is needed is a CAM cell that provides a size (cost) advantage over that provided by a SRAM-based CAM cell, but avoids the problems associated with conventional DRAM-based CAM cells.